In microelectronics and in solar cell devices, silicide is widely used to make contact to the silicon substrate and make contact to the conductor metal. A silicide layer is formed by depositing a pure metal thin film directly on top of the silicon substrate, usually by physical vapor deposition processes, such as sputtering or evaporation, and followed by a thermal annealing process. Then, an additional barrier layer, such as TiN, W, Ta, TaN, may be deposited on the formed silicide layer, also by mostly vacuum processes, before deposition of the main conducting metal, generally copper lines. However, this approach is cost prohibitive for solar cell applications due to the use of vacuum based processes.
Silicide processes also have been widely used to form silicide contacts on the gate and source/drain of metal oxide semiconductor field effect transistors (MOSFETs) or on the emitter, base, and collector of bipolar devices. For the formation of the silicide contacts, the process generally includes forming a stable metal compound by reacting silicon and metal and reduces the sheet and contact resistance at contact regions. Such a process is useful in obtaining high performance semiconductor devices.
In addition, silicide processes or a self-aligned silicide processes have been used in fabrication of many logic devices. However, in the fields of next generation high-speed complementary metal oxide silicon (CMOS) logic devices and embedded dynamic random access memory (DRAM) devices formed by combination of logic devices and DRAM devices, there has been a need for the development of new silicide materials that can provide better results than TiSi2 and CoSi2 which have been mainly applied in conventional silicide processes.
Recently, nickel monosilicide (NiSi) has been proposed and studied as a silicide material suitable for a next generation ultralarge-scale integrated (ULSI) semiconductor process.
For instance, U.S. Pat. No. 7,153,770 describes a method of manufacturing semiconductor device, in which a Ni/Co alloy is annealed to form nickel monosilicide (NiSi), followed by a W deposition on the silicide. In particular, the patent describes using a thin Mo layer before putting down Ni on Si to form an inhibition layer for NiSi formation to get better silicide uniformity. However, both processes are vacuum based.
U.S. Pat. No. 6,251,777 describes a thermal annealing method, in which Si and silicide forming metal(s) are annealed to form silicides. Silicide formation by depositing extra silicon layer to react with metal, which is also a vacuum based process.
U.S. Pat. No. 4,907,052 describes semiconductor tandem solar cells, in which NiSi is formed on Si, and a diffusion layer. In particular, the patent describes a metal silicide layer as a blocking layer between p-Si and n-Si dopants interdiffusion.
U.S. Pat. No. 5,166,770 describes silicide structures, in which a diffusion barrier is formed prior to a conductive metal deposition. In particular, the patent describes the traditional self-aligned silicide process for MOSFET devices using Ti, Ta, or Mo silicide as contact to p-Si region of the device, which is also a vacuum based process only.
This disclosure illustrates a method to form a silicide layer and a diffusion barrier layer simultaneously from a metal alloy layer on silicon substrates during a thermal annealing process, with the metal alloy layer deposited by either solution or vacuum processes. This significantly reduces the process steps and reduces cost of processing.